1. Field of the Invention
The present invention relates to a circuit for preventing invalid output in a flash memory device, and more particularly, to a precharge circuit for preventing invalid output pulses caused by current sensing circuits in the flash memory devices.
2. Description of the Prior Art
Nowadays, many kinds of electrical products are invented and manufactured each day, and these new products usually need high processing speed than before. A key point for upgrading the processing speed is to effectively enhance the access time from data storage, such as decrease the transmission delay of the volatile or non-volatile memories. A major disadvantage of the volatile memories, such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) is that they lose all their stored memory if power is turned off. However, it is important for some memory systems to retain their data even the power is off. Non-volatile memories, such as ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrical EPROM), and flash memory are another class of memories that are developed to prevent programmed data from being lost. Typically, the manufacturer or user can program their non-volatile memory based on requirements, and the programmed data can be stored for a long time interval.
Flash memory is a relative new generation of the non-volatile memories that is derived by a technology similar but advanced to the EPROM device. All the skilled persons know that many advantages offer by the flash memory. For example, the flash memory is electrically re-programmable a few times ranging up to many thousand times. Furthermore, the flash memory can be packaged in the low cost plastic package, and the flash memory also can be used in high-density sockets that will be basic requirements in the future.
Current sensing circuits are commonly used for generating outputs signals when accessing data from the flash memories. However, invalid output pulses are usually detected in the read-cycle of the flash memories. Referring to FIGS. 1A and 1B, which respectively illustrates the functional and detail diagrams of a conventional current sensing circuit (please refer to the U.S. Pat. No. 5,386,158). In FIG. 1A, a sensing enable signal (SE) input to a current mirror 11 is used to retrieve the programmed data (S.sub.o) which is programmed in a cell array 12 beforehand. Typically, the memory cell that is programmed to conduct current indicates logic 1 (usually is designated to be V.sub.cc), and the memory cell that is programmed to prevent from conducting current is used to indicate logic 0 (usually equals to the ground's voltage level). When the read-cycle starts, a current generated by the current mirror 11 will detect the selected memory cell of the cell array 12. Therefore, the logic-state of the selected memory cell is determined by the current through a bit line (BL).
FIG. 1B represents a detail circuit structure of the current sensing circuit in FIG. 1. A reference voltage (V.sub.ref) connects with the gate of the NMOS transistor 105 is used to sink a reference current (I.sub.ref). Please note that the BL is reset to logic 0 before each read-cycle starts. Accordingly, when the BL is reset and the SE is 0, a PMOS transistor 101 will be conducted but an NMOS transistor 104 is turned off. The voltage level of the node B is thus risen to logic 1, and both of the PMOS transistors 102 and 103 that consists the current mirror 11 are not turned on. When the read-cycle starts, SE will rise to logic 1 to conduct the NMOS transistor 104. The NMOS transistor 104 is treated as a current switch to conduct the current from the current mirror 11 to the selected memory cell through BL. The PMOS transistor 102 and 103 (i.e. current mirror 11) will turn on and the voltage level of the node B will fall. As noted, the BL is detected when the read-cycle starts at the same time. If the selected memory cell is not conductive, there will be no current flowing through the PMOS transistor 102 to the NMOS transistor 104. Because the I.sub.ref indicates a constant current, the voltage level of the node A will be pulled down to logic 0. Thus, the output S.sub.o is also logic 0.
On the other hand, when the selected memory cell is conductive, there will be a significant current flowing through the PMOS transistor 102 and the NMOS transistor 104 into the selected memory cell. Because both the PMOS transistors 102 and 103 are conductive, a current I.sub.c with the same amount flowing through the PMOS transistor 102 will also appears at the node A. Because the current I.sub.c is designated to be much larger than I.sub.ref, the voltage level of the node A will be pulled up to be logic 1, and S.sub.o is also logic 1 after amplifying by two series inverters 106 and 107.
Although the conventional current sensing circuit can be employed to access programmed data from the cell array 11, however, a longer access time is required for waiting the accessed voltage levels to be stable. Referring to FIG. 3A, which illustrates a waveform diagram representative of an output waveform derived from the circuit in FIG. 1B. An invalid logic 1 is caused by a current directed into the cell array 12 when BL being set. Therefore, each time when the read-cycle begins, a current flowing to BL will induce the current mirror to generate an undesired current to charge the node A, and the invalid logic 1 is thus obtained at S.sub.o. A curve indicated by dot-lines is used to represent the output waveform at S.sub.o when the selected memory cell is not conductive. Another curve that is indicated by solid-lines is used to describe the output waveform S.sub.o when the selected memory is conductive. It is clearly that S.sub.o is unstable until t.sub.2, and there is a significantly time delay (from t.sub.1 to t.sub.2) for waiting. Typically, t.sub.1 is about 10 nano seconds, and t.sub.2 is about 20 nano seconds. Sometimes, although S.sub.o outputs a stable logic 1 before t.sub.1, however, the invalid logic 1 is clearly an error when logic 0 is programmed. A need has therefore been arisen to disclose a circuit, in which the access time delay of the current sensing circuit here can be significantly reduced for achieving the requirement of high operation speed.